This invention relates to cleaning of semiconductor wafers.
Semiconductor wafers for the microelectronics industry are produced by first slicing thin wafers from a crystal ingot. After slicing, the wafers undergo a lapping process to give them a somewhat uniform thickness. The wafers are then etched to remove damage and produce a smooth surface. The final step in a conventional semiconductor wafer shaping process is a polishing step to produce a highly reflective and damage-free surface on at least one face of the semiconductor wafer.
The wafers must be cleaned between the lapping and etching steps to remove contaminants such as lapping grit. If the cleaning process is not effective, the surfaces of the wafer will be stained with fine lapping grit residue. Such residual grit may cause contamination problems during electrical device fabrication.
Cleaning of lapped silicon wafers is generally done in ultrasonic tanks using a caustic solution with or without a surfactant to assist in wetting and dispersing dirt. The total processing time to produce sufficiently clean wafers may be thirty or more minutes.
A disadvantage of the duration of the cleaning process is that prolonged exposure to ultrasonics causes damage to the wafers. The extensiveness of the damage increases as the exposure time to the ultrasonics increases.
Another disadvantage of the cleaning process duration is delay in providing feedback information to the lapping operator concerning the quality of the lapped wafers (e.g., Total Thickness Variation measurements, presence of scratches, etc.). Such information allows the operator to make any needed corrective adjustments to the lapping process for avoiding damage to additional wafers, but can generally only be provided after the wafers are cleaned. The longer the delay in providing the feedback information, the larger the number of damaged wafers before corrective actions can be taken.